5th Power Analysis & Design Symposium 2016
The 5th Power Analysis & Design Symposium took place on April 21st, 2016 in Eching near Munich (Germany). Also this year we organized an Open-Lab, in the afternoon prior the Symposium, where participants could use our measurement equipment live and even bring their own designs to be tested. You can download the flyer with all important information.
Current sources are everywhere around us. Especially LED drivers gain significant importance and are rapidly replacing other luminaries in various markets and applications. While most literature and scientific work is dealing with stability analysis of common voltage sources, little can be found on the specific aspects on how to properly apply common stability criteria to current sources. The load of a current source is an active part of the power conversion system that can hide issues with stability and common design margins.
This lecture will walk you through an entire development process from simulation to design validation, highlighting common pitfalls and introduce techniques to unravel hidden stability issues using real-world design examples.
The current growth of always connected electronic devices keeps on pushing the demand for smaller power footprints and power efficiency to the limit. Synchronous DC-DC converters are a constituent part of any electronic system, and are therefore directly linked to the optimization of the footprint, and efficiency when it comes to digital power conversion. While the efficiency of a synchronous DC-DC converter, such as a buck converter, is nonetheless dependent on several variables, being one of the major contributors is the body diode conduction losses. We will demonstrate in this presentation, how to implement an algorithm in an XM4200 ARM Cortex M4F microcontroller, that targets the minimization of body diode losses in the power switching devices.
This algorithm implemented in an ARM Cortex M4F will have low computational requirements and will take advantage of the first on the market 150 pico second high-resolution dead-time control. The algorithm follows a sensorless topology, which offers a reduced system footprint for the world of connectivity, while taking advantage of the unique combination of a high-resolution duty cycle, and a high resolution dead-time control to improve the overall efficiency of the DC-DC converter. A complete organization of the microcontroller resources to implement the algorithm is going to be demonstrated and presented. The algorithm is used to optimize the dead-time of the converter on both ON-to-OFF and OFF-to-ON state transitions. The final results are demonstrated using the XMC4200 ARM Cortex M4F microcontroller and a DC-DC Buck Converter. The low computation algorithm will improve the converter efficiency while using the first time ever 150 pico second resolution dead-time, in more than 1% versus the same algorithm with low resolution dead-time, and in more than 3% when compared with a fixed dead-time algorithm.
Modern digital power controllers do not only improve the power efficiency of converters, they can also enhance their reliability and availability. New features like volt-second-balance, matched cycle-by-cycle current limiting, digital current sharing and nonlinear gain control for fast transient response can only be realized by digital controllers.
The volt-second-balance helps equalizing the current in the power transformer to avoid successive accumulation of magnetic flux, thus avoiding transformer saturation and overheating. Matched cycle-by-cycle current limiting avoids transformer imbalance during over current condition. Digital current sharing provides accurate and EMI-robust control of converters working in parallel. The digital share bus takes a similar control approach to the analog share bus. However, the main difference is at the communication level. Each power supply outputs a digital word (rather than an analog voltage) which is proportional to the current that the power supply is delivering. The bigger the word, the bigger the current that unit is delivering to the load. Each unit senses the word that appears on the bus, and compares it to it’s own word. This comparison is performed in a bit-by-bit routine, starting with the MSB. Once a unit senses that it’s word is smaller than the word on the bus, it knows that it must increase its contribution to the system load.
Nonlinear gain enhances the system response on fast loads transients. During a transient condition, the digital compensator acts on the error voltage and adjusts the control input to correct for the error. This may take several switching cycles, especially during a transition from DCM to CCM. In such cases, a boosted error signal aids in reducing the settling time and can even avoid an overshoot.
Every product brought to the market must pass certain EMC tests. An essential design step for a proper functioning DC/DC switching converter is the selection of optimal components. In addition the PCB layout of the converter circuit and the filter circuits are critical for the EMC properties of the converter. In this lecture we will show how to calculate input and output filters for switching power converters and will present the influence of PCB layout issues, part selection and filters based on real-life EMC measurements.
Power management systems can be very complex these days. Many interdependent supply rails, very demanding dynamic requirements (e.g. FPGA core), space restrictions, tight cost budgets, etc. are challenging hardware engineers responsible for power supply concepts and implementations. “Digital Control“ is a key topic since many years and possible advantages have been widely discussed, but one important aspect mostly remains unsaid, it means adding a lot of complexity.
This presentation gives a quick overview on LTC´s Power System Management (PSM) concept which combines proven technology (e.g. fast analog control loops with current/voltage mode control and non-linear slope compensation) with add-on digital features. It then focuses on a new PSM buck controller, the LTC3884, that offers adjustable loop compensation via PMBus. Simulations and Bode 100 measurements will be used to visualize how this feature can be used to easily optimize dynamic performance of a DC/DC converter.
- 04/04/2019 8th Power Analysis & Design Symposium 2019
- 04/26/2018 7th Power Analysis & Design Symposium 2018
- 04/26/2017 6th Power Analysis & Design Symposium 2017
- 05/06/2015 4th Power Analysis & Design Symposium 2015
- 05/15/2014 3rd Power Analysis & Design Symposium 2014
- 05/22/2013 2nd Power Analysis & Design Symposium 2013
- 05/03/2011 1st Power Analysis & Design Symposium 2011